1. Field of the Invention
The present invention relates to an electrode for penetration or embedding (hereinafter, which will be referred to a “through electrode” or “embedded electrode”, respectively, and both of which will be referred to a “through/embedded electrode”).
More particularly, the present invention relates to a through/embedded electrode to be formed in a hole or opening of a substrate (hereinafter, a structure including the substrate and the through/embedded electrode will be referred to an “electrode structure”), a material for the through/embedded electrode, and a method of forming the through/embedded electrode.
2. Description of the Related Art
As a method for forming a through electrode in an opening of a substrate which is essential for three-dimensional stacking of semiconductor chips, the following three conventional methods are generally known. However, all of them have problems for practical use because of the following difficulties:
The first method is the conformal copper plating as the representative example of liquid phase deposition. With this method, a dense thin film of copper is formed along the inner wall of an opening using an electroless plating solution. In this case, the thin film of copper covers the whole inner wall of the opening only, and the inside of the opening is not completely filled. This method has been already used in mass production; however, a recess is formed on one end face of a through electrode thus formed and therefore, a larger connection line pattern than the diameter of the through electrode is necessary in the alignment step of wiring. As a result, it is difficult to realize high-density wiring with the through electrode formed by this method.
The second method is the copper metal filling method. With this method, which is a typical example of vapor deposition, not only an expensive ionization sputtering apparatus or a metal CVD apparatus is required but also a processing time is long and fabrication cost is high. Moreover, since the whole through electrode is made of dense copper, the through electrode has a high modulus of elasticity. In addition, since the thermal expansion coefficient difference between the through electrode and a semiconductor substrate (e.g., silicon wafer) is large, an excessive internal stress occurs due to thermal shock induced by temperature cycling during the fabrication steps. For this reason, a crack may be formed in the semiconductor substrate.
The third method is the conductive metal paste filling method. With this method, a monomer is used as a diluent for a conductive metal paste and therefore, a lot of organic residues are left after drying and the conduction resistance of a through electrode is high. In the aftermath of this, not only restriction is applied to the circuit design but also the electrical characteristics are likely to be unstable.
Many improvements of the aforementioned three conventional methods have been disclosed, where the number of the proposed improvements for the aforementioned third method is relatively large.
For example, Patent Literature 1 (JP Patent Publication No. 2011-054907) discloses a method of depositing a suspension of metal powder in openings using a pressure and a filter. FIG. 4 corresponds to FIG. 1 of Patent Literature 1. In this figure, a substrate 101 having through holes 102 is disposed above a filter 140. The reference numeral 130 denotes a suspension of fine metal particles. By depressing a piston 120, the suspension 130 of fine metal particles is pushed into the through holes 102 and deposited. After taking the substrate 101 out and drying the same, a conductive paste is embedded into the through holes 102 and cured, resulting in through electrodes. With this method, the ratio of the metallic component of the through electrodes is raised by depositing metallic components twice, thereby contributing to the improvement of the conductivity of the through electrodes.
Patent Literature 2 (JP Patent Publication No. 2011-071153) discloses a method where a metal paste is coated on a wafer substrate with a blade while applying vibration to the metal paste, and at the same time, a suction pressure is applied to the wafer substrate from the opposite side thereof, thereby depositing the metal paste in the openings and sintering the metal paste thus deposited. FIG. 5 corresponds to FIG. 1 of Patent Literature 2. With this method, the packing density of the metal paste is raised to ensure the conductivity of the through electrodes.
Patent Literature 3 (JP Patent Publication No. 2009-277927) discloses a method where after coating a small amount of a metal paste, a molten metal is flowed through by applying heat and high-speed vibration in a vacuum atmosphere, thereby depositing the metal.
With the methods of Patent Literatures 1 to 3, the object of each of the methods is achieved; however, taking the damage applied to existing circuit patterns during the processing processes, attachment and detachment of an auxiliary material (supporting glass substrate, etc.), and all the implementation steps of a semiconductor device into considerations, these methods have a hindrance to practical use.
Regarding through electrodes, it is the biggest challenge in accomplishing performance sophistication and quality assurance of products to prevent reliability lowering due to cracks or the like which is induced by a thermal expansion coefficient difference between the materials used during alternating temperature cycle of fabrication processes, and to prevent signal transfer characteristic degradation due to the conductivity of a material or materials constituting the electrode.
Further, attention should be paid to the request for higher density arrangement also, which is induced along with miniaturization of the semiconductor manufacturing technology. To meet this request for higher density arrangement, reliability and signal transfer characteristic equivalent to those before size reduction are necessary even when reducing the size of a through electrode.